Staff CPU Design Verification Engineer

Job Title: Staff CPU Design Verification Engineer Company: SiFive Job Category: Machine Learning Roles & Responsibilities: As the pioneers who introduced RISC\-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC\-V to the highest performance and most data\-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC\-V has no limits.* Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. Job Description: As a Staff Hardware Engineer in Design Verification of CPU, you will own verification strategy and execution for complex out‑of‑order (OOO) processor and cache/memory subsystems . You will define methodology, lead testplan creation, and drive verification of speculative execution, memory ordering, and coherence features from architecture through tape‑out. Key Responsibilities ------------------------ Testbench Architecture \& Implementation + OOO core pipeline (including scoreboards and scoreboard‑driven checking). + Cache/memory hierarchy, TLB/IOMMU, and coherence protocols. * Develop reusable verification components: generators for OOO stress (back‑to‑back branches, deep speculation, dependency patterns), monitors, scoreboards, and protocol checkers. * Model reference behavior (ISA / memory model) for end‑to‑end checking of: * Write and maintain assertions for key OOO properties, e.g.: * Lead debug of complex OOO bugs: Methodology, Infrastructure, and Leadership Work Location: Telangana, India Availability: Full time

Required Qualifications: Education / Experience * BS/MS/PhD in EE/CE/CS or related field. * Typically 8 \+ years in ASIC/SoC/IP design verification , with significant experience on out‑of‑order CPU or advanced core projects. Technical Skills * Strong expertise in System Verilog and UVM . * Direct verification experience with OOO CPU micro‑architecture , including several of: + Memory consistency models (e.g. RVWMO, TSO) and how they map onto hardware. + Coherence protocols and cache hierarchy (L1/L2\+, inclusive/exclusive, write‑back). * Hands‑on experience with: Key Skills: Machine Learning Salary: Not disclosed